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Applied AI Engineer
Summary by AIEngineer.careers
Applied AI Engineer is a AI Engineer role (full-time). with Silimate. in SAN FRANCISCO, US. Compensation shown: $140K–$220K. Imported listing (source: zerogtalent.com). Apply on the employer's site (zerogtalent.com).
Imported listing (source: zerogtalent.com) · Apply on zerogtalent.com
SAN FRANCISCO · US
$140K–$220K
Full-time
The sections below reproduce the third-party job description for reference. AIEngineer.careers does not write or control this text.
Imported job description
Sourced from zerogtalent.com
Silimate is looking for an Applied AI Engineer to build AI-native core tools and agents for frontend chip design workflows. The role involves developing AI models, core infrastructure, and shipping software to semiconductor enterprise customers. You will own key product decisions, translate user feedback into features, and help shape the product roadmap. Candidates should have strong Python, C++, and PyTorch skills, plus hands-on experience with LLMs, foundation models, and ML pipelines.
Responsibilities
- Develop AI models, core tools, and infrastructure that ship to Fortune enterprises and chip unicorns
- Make architectural decisions for key product features
- Translate user feedback into product updates/features
- Plan core product roadmap and strategy
Requirements
- Highly skilled with Python, C++, PyTorch/torch
- Strong understanding of traditional ML models, LLMs, foundation models, and agents
- Experience building ML pipelines
- Experience fine-tuning and benchmarking LLMs/foundation models
- Excited about applying AI/ML techniques to chip design
- Good at shipping high-quality code quickly
- Resilient, data-driven, and works from first principles
- Have shipped product using LLMs, foundation models, and/or agentic workflows
Silimate
Mountain View · US · 8+ employees
Silimate is an AI-native company that develops a chip design copilot to assist engineers in accelerating frontend chip design and debugging processes. The company provides AI-driven agents that help chip teams automate functional verification and optimize Power, Performance, and Area (PPA) targets.
